SUSS MicroTec

Wafer size
Wafer bonding at pressures 5e-5 to 3e-3 Torr and 50*C to 550*C
Power
up to 2000 V[2]
Vacuum
5e-5 to 3e-3 Torr[1]
Performance
+/- 5 degrees[2]
The SB 6 utilizes a robust vacuum chamber that can achieve pressures from 5e-5 to 3e-3 Torr. The system provides independent upper and lower substrate heating over a temperature range of 50 °C to 550 °C, with programmable pressure control up to 20 kN of force. A wafer-stack transfer arm moves the aligned wafer pair into and out of the chamber. For aligned bonding, the SB 6 is used with the SUSS MA6 or BA6 aligner, which positions the substrates before bonding.[1][2][3][4]
During a bonding cycle, the aligned wafer stack is placed between two bond heads. The chamber is evacuated or backfilled with a controlled gas, and the desired temperature and force profiles are applied according to a stored recipe. The bond heads can be exchanged: one head is dedicated to anodic bonding (with a voltage supply up to 2000 V) and another for fusion bonding. The system supports multiple process steps within a single recipe.[2][3]
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Permanent bonding, such as fusion or direct bonding, creates a final joint intended to last through the device lifecycle. Temporary bonding uses a removable adhesive layer to mount a device wafer to a carrier, allowing subsequent processing (e.g., thinning, via etching) before the wafer is debonded. Substrate bonders of this class can be configured for either mode by controlling the bonding adhesive, temperature, and force profile.
The class typically supports thermocompression bonding, adhesive bonding, eutectic bonding, fusion (direct) bonding, and anodic bonding. The specific processes depend on the temperature range, force capacity, vacuum capability, and alignment precision of the machine. Process recipes are user‑programmable to accommodate different materials and bond requirements.
Alignment accuracy directly impacts electrical connectivity in stacked devices. In processes such as wafer‑to‑wafer bonding for three‑dimensional interconnects, misalignment can cause shorts, open circuits, or increased resistance. For MEMS capping, poor alignment may compromise hermetic sealing or optical access. Thus, class‑level machines emphasize high‑resolution optical alignment systems and sub‑micron stage repeatability.
Common substrate materials include silicon, glass (borosilicate, quartz), compound semiconductors (GaAs, InP), silicon carbide, sapphire, and various dielectrics. Temporary carrier wafers may be made of silicon or specialized glasses. The class can also handle substrates with pre‑existing layers such as metal pads, dielectric coatings, or release layers.
Critical parameters include bonding temperature and ramp rate, applied force and contact pressure, chamber vacuum or gas atmosphere, surface cleanliness and activation conditions, and alignment offset. Process control ensures uniform bond interface, minimal void formation, and prevention of thermal stress or delamination. Users typically develop recipes that specify the sequence and setpoints for each of these parameters.
The following facts about the SB 6 are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.
No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the SB 6 are on record.
Answerable by: OEM historical records or a trade-press announcement
The control-system platform and OS era of the SB 6 are not on record.
Answerable by: an engineer who operated it or OEM installation records
No publicly documented failure modes or field errata for the SB 6 are on record.
Answerable by: a field service engineer, process engineer, or maintenance technician
The process node or technology generation of the SB 6 is not on record.
Answerable by: an OEM datasheet or a fab qualification report
No publicly documented compatible parts, consumables, or accessories for the SB 6 are on record.
Answerable by: an OEM parts catalog or a service engineer
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Last updated Sep 30, 2026.
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